The present invention relates to a data transmission circuit for use in semiconductor memory devices, and more particularly relates to a data transmission circuit for transmitting data signals from a data input buffer to a pair of input/output (hereinafter will be referred to as an "I/O") bus lines in a CMOS dynamic random access memory (hereinafter will be referred to as a "DRAM") device.
Conventionally, a CMOS DRAM device includes the data input buffer which is activated in a write cycle and converts TTL (Transistor - Transistor Logic) level input data signals to CMOS logic level data signals. The data input buffer supplies true and complement output data signals on a pair of data bus lines, respectively, and signals on the pair of data bus lines are respectively sent to a pair of I/O bus lines. Thereafter, the true and complement signals on the I/O bus lines are respectively transmitted on a pair of corresponding bit lines via a pair of transfer gates respectively coupled to the I/O bus lines and turned on by a column address signal via a sense amplifier. One of the data signals on the bit line pair is written into one memory cell selected by a row address signal provided by a row address decoder.
However, since in high density DRAM devices, for example, in such devices as a 1 mega-bit DRAM, both the data bus line pair and the I/O bus lines pair extend a long distance from the data input buffer to the bit line pair in view of the circuit arrangement, the data input buffer must bear the burden of driving one of the data bus line pairs having parasitic capacitance of approximately 1.5 pf per line and the corresponding I/O bus line having about 3 pf to 4 pf per line as a load.
To assist in understanding the disadvantages which plague prior art devices, a data transmission circuit is shown in a block diagram form in FIG. 1. Referring to FIG. 1, the data signal read into the circuit through the data input buffer 10 is outputted as a pair of true and complement MOS logic level data signals DIN and DIN, and the signals DIN and DIN are respectively coupled to a pair of data bus lines 11 and 12. The signals DIN and DIN are respectively sent on the I/O bus lines 13 and 14 through a pair of transmission transistors 1 and 2 which are turned on by the transfer gate control clock signal on a gate line 16 generated with the combination of a write enable signal and column address signals. The data signals transmitted on the I/O bus lines 13 and 14 are respectively sent on a pair of bit lines 61 and 60 through a pair of transmission transistors 44 and 43 constituting a transfer gate 40 turned on by the column address signal on a gate line 41 and through a sense amplifier 50. Thereafter, one of true and complement data signals on the bit lines 61 or 60 are written into a memory cell 63 or 62 by a row address signal on a row address line 65 or 64.
An I/O sense amplifier 30 works only in a read cycle amplifies one of true and complement data signals on the I/O bus lines 13 and 14 read out from the memory cells. An equalizer circuit 20 begins the operation for equalizing the I/O bus lines 13 and 14 at the precharge time of read and write cycle.
Therefore, the data transmission circuit shown in FIG. 1 must drive the large parasitic capacitance of the data bus line and its corresponding I/O bus line as a load in order to write data information into a memory cell 62 or 63. Thus, the data input buffer 10 must include a large size current drive transistor at the output stage thereof in order to charge the large parasitic capacitance and as a result, a low rate transfer speed and the large power consumption are effected.
One way of decreasing the parasitic capacitance of the I/O bus line providing the largest capacitance was to divide on chip all memory cells into several blocks including a certain number of memory cells according to the integration and density of memory cells. Such increase of the number of divided blocks causes an increase of I/O bus line pairs and that of their corresponding transmission transistors.
In a write cycle for reading the data information into the memory cell array, however many are the I/O bus line pairs due to the number of such divided blocks, there is no problem because only one of I/O bus line pairs is selected and then one of the data signals on the selected I/O bus line pair is stored in an addressed memory cell. However, the larger the integration density of memory cells, the more serious is the problem of testing the memory cells when the memory device is manufactured. That is, the test time for writing data information into all memory cells and for reading the sotred information out from each memory cell increases greatly according to the increased density of memory cells. Therefore, to achieve a high speed test of memory cells, a plurality of data bits must be written into addressed memory cells and read out from those memory cells. In this case, since the I/O bus line pairs must be coupled to the data input buffer in the same numbers as the number of data bits written into memory cells, the load burden of the data input buffer will be increased by the number of such data bits. Finally the size of the transistors for driving the I/O bus pairs at the output stage of the data input buffer will be increased to accommodate the increased parasitic capacitance and as a result, the chip size will be increased.